1. Field of the Invention
The present invention relates to an apparatus for increasing the data transfer rate of a computer system. More particularly, the invention relates to an apparatus for predicting portions of the computer""s address lines during a burst transfer cycle.
2. Description of the Related Art
The personal computer industry is evolving quickly due to the user""s demands for faster, smaller, and more powerful computers. To flexibly accommodate the needs of a variety of applications, a personal computer typically has an expansion bus such as an extended industry standard architecture (EISA) bus for interfacing the microprocessor with one or more optional external plug-in logic circuit boards.
Derived from the original industry standard architecture (ISA) standard which is still in use today, all EISA performance and function enhancements are superset features of the ISA bus standard. The EISA specification provides for a variety of cycle types to cover the range of speed and complexity requirements for different applications. The EISA bus specification describes all parameters that must be followed for any device to communicate with an EISA bus and is fully disclosed in Appendix A of U.S. Pat. No. 5,101,492, hereby incorporated by reference.
Under the EISA specification, the standard EISA transfer cycle requires two clock cycles. However, bus masters are permitted to generate EISA burst cycles which require only one clock per transfer after the first cycle. The burst transfer cycle allows a master running at the full data rate to transfer one 32-bit data element on every rising edge of the bus clock (BCLK), whose frequency is typically 8 to 8.3 MHz. At an 8.3 MHz BCLK frequency, the computer system can burst transfer data with up to a 33 megabytes per second transfer rate.
The EISA standard has recently been extended to include two new burst transfer modes called the enhanced master burst (EMB) transfer modes. The first extension, known as the EMB66 protocol, provides up to a two-fold increase in the data transfer rate when compared to existing EISA bus master burst rates while maintaining the existing bus clock frequency. The second extension, known as the EMB133 protocol, provides upto a four-fold increase in data transfer rate. The two-fold performance increase in the EMB66 protocol is achieved by transferring one 32-bit data element on each of the rising and falling edges of the BCLK. The EMB66 transfer protocol thus provides for burst cycles with up to 66 megabytes per second data transfer rate.
The EMB133 protocol extends this performance improvement one step further by transferring 64-bits of data on each of the rising and falling edges of BCLK. The EMB133 protocol uses the EISA address and byte enable lines for data transfer in addition to the existing data bus to effectively increase the width of each EISA data transfer from 32-bits wide to 64-bits wide. As all data operands consist of 64 bits in the EMB133 mode, the EMB133 transfer protocol can thus transfer burst cycles with up to 133 megabytes per second data transfer rate. As can be seen, the newly defined EMB extensions to the EISA bus specification provide for increasing the burst transfer rate of EISA bus masters.
The EMB66 and EMB133 protocols maintain compatibility with existing EISA expansion boards by being supersets of the existing EISA bus master protocol. Expansion boards. implementing EMB66 and EMB133 protocols initially default to the existing EISA bus master protocol until explicitly enabled during the boot process. The new protocols require both the master and the slave to indicate support for the new protocols at the initiation of each burst transfer via two new signals, EMB66* and EMB133*, which are assigned to previously reserved pins on an EISA connector. EMB66* and EMB133* are active low open collector signals which should be terminated through pull-up resistors. The use of an open collector signal allows one signal line to be shared between the EISA master and the slave during the configuration handshake.
Under the EMB66 extension, full backward compatibility with the original EISA timing parameters are maintained such that an EMB-capable system will not violate the EISA parameters. However, the EMB extension requires additional robustness beyond the EISA specification. For instance, an EMB system is required to meet slightly more stringent alternating current (AC) timing parameters in order to provide the necessary margin for the higher bandwidth. Many existing devices designed for the original EISA interface standard may not meet the tighter timing margin required of an EMB system. A complete modification of all devices which interface with the EISA bus is impractical due to the cost and development time delay associated with such a conversion. Further, the use of higher speed logic families to meet the tight timing tolerance of the EMB extension may be cost-prohibitive. Thus, it is desirable to provide a circuit which relaxes the tighter timing margin imposed on the EMB-capable system so that the devices designed for the original EISA standard can still be used in designs that support the EMB extension.
The technique of transmitting data on the rising and falling edges of the BCLK signal also presents another problem. The EMB protocol transmits either two 32-bit words or two 64-bit words per BCLK period even though only one address can be indicated on the EISA bus per BCLK period. Under such condition, the address line LA2 of the EISA bus only represents the first 32-bit word of the pair and does not reflect the address of the second 32-bit word. Thus, a need exists for a circuit that can automatically increment the address line LA2 to properly direct the transfer of the second 32-bit data in the EMB mode.
The present invention provides a burst transfer cycle for transferring data in accordance with the EMB extension to the EISA specification. The tight timing constraints of the. EMB extension are relaxed by predicting and making available in advance certain information, namely the address signals, to the bus interface of the slave devices.
The address signal prediction is based on the EMB protocol requirement that EMB cycles transfer data with addresses following a contiguous and ascending order. By using this deterministic address order, the recipient of the EMB mode data transfer predicts the next address of the sequence. This prediction is performed by a decoder which observes the control signals of the expansion bus to detect the start and the end of the EMB burst transfer cycle and instructs a counter to increment, thus generating predicted address signals. The counter stores the initial address signals of the expansion bus at the start of the EMB cycle and increments the address signals during the EMB cycle.
As the address signals to the bus interface logic of the slave device can be either the predicted address from the counter during the EMB cycles or address signals from the expansion bus during non-EMB cycles, a multiplexer device is used to select between the address signals. The multiplexer couples either the predicted address signals to the multiplexer output during the EMB burst transfer cycle or the address signals of the EISA bus to the multiplexer output when the computer system is not performing the EMB burst transfer cycle.
Because the address of the expansion bus during an EMB transfer cycle reflects only the address of the first 32-bit word in the pair being transferred, the low order address bits of the second 32-bit word are predicted and merged with the address placed on the bus in order to properly index the second word. The slave of the EMB mode data transfer predicts the address of the second 32-bit data. The prediction of the low order address signal is performed using a second counter which is incremented automatically during the EMB mode transfer. The predicted low order address bits from the second counter are then merged with the address bits of the first 32-bit word before being used to index the second 32-bit word.